Datasheet

Real Time Clock (RTC)
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 377
20.4.1.4 Counter Control Register (RTC_CCR)
MEM Offset (B0000400) 0Ch
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell
31:4 RO 28'h0 Reserved (RSVD1)
Reserved
3 RW 1'h0 RTC WEN (RTC_WEN)
This allows the user to force the counter to
wrap when a match occurs instead of waiting
for the max count
2 RW 1'h0 RTC EN (RTC_EN)
Allows the user to control counting in the
counter 0 = counter disabled 1 = counter
enabled
1 RW 1'h0 RTC MASK (RTC_MASK)
Allows the user to mask a generated
interrrupt 0 = interrupt mask 1 = interrupt
mask
0 RW 1'h0 RTC IEN (RTC_IEN)
Allows the user to disable interruput
generation 0 = interrupt disable 1 = interrupt
enable
20.4.1.5 Interrupt Status Register (RTC_STAT)
MEM Offset (B0000400) 10h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell
31:1 RO 31'h0 Reserved (RSVD1)
Reserved
0 RO 1'h0 RTC STAT (RTC_STAT)
This register is the interrupt status 0 =
interrupt is inactive 1 = interrupt is active