Datasheet

Real Time Clock (RTC)
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
372 Document Number: 333577-002EN
For accessing any registers in RTC block, both APN Clock (pclk) and counter clock
(rtcclk) should be running and the frequency of the APB Bus clock must be greater
than three times the frequency of the counter clock. If CCU_SYS_CLK_SEL register in
SCSS is configured to choose rtcclk for system clock, then CCU_RTC_CLK_DIB register
in SCSS shall be configured for div-by-4 or lower, in order to ensure that all register
accesses to RTC block are properly synchronized to counter clock (rtcclk) domain.
After writing a register, firmware has to wait for atleast 1 rtcclk input before clock
gating pclk. Interrupt status bit (rtc_stat) in RTC_STAT/RTC_RSTAT register will get
cleared 1 rtcclk period after reading RTC_EOI register. Alternatively firmware can
choose to ignore the interrupt status register and rely only on the rtc_intr line
interrupt for interrupt status, which gets cleared immediately after reading RTC_EOI
register.
20.3 Use
The RTC allows the user to disable interrupt generation and also to mask a generated
interrupt.
For accessing any registers in RTC block, both APN Clock (pclk) and counter clock
(rtcclk) should be running and the frequency of the APB Bus clock must be greater
than three times the frequency of the counter clock. If CCU_SYS_CLK_SEL register in
SCSS is configured to choose rtcclk for system clock, then CCU_RTC_CLK_DIB register
in SCSS shall be configured for div-by-4 or lower, in order to ensure that all register
accesses to RTC block are properly synchronized to counter clock (rtcclk) domain.
After writing a register, firmware has to wait for atleast 1 rtcclk input before clock
gating pclk. Interrupt status bit (rtc_stat) in RTC_STAT/RTC_RSTAT register will get
cleared 1 rtcclk period after reading RTC_EOI register. Alternatively firmware can
choose to ignore the interrupt status register and rely only on the rtc_intr line
interrupt for interrupt status, which gets cleared immediately after reading RTC_EOI
register.
20.3.1 Clock and Calendar
The 32bit counter is intended to provide Clock and Calendar functionality, the
capabilities differ depending on the chosen frequency of the RTC clock as described in
the examples below.
Using a 1 Hz RTC clock the following capabilities are exposed:
• Counter increments every second
• Counter wraps in 2
32
-1 seconds (~136 years)
• Counter can be used to store Time and Date in the Unix Time format defined
as the number of seconds since 00:00:00 UTC on 1 January 1970 (the epoch)
Using a 32.68 kHz RTC clock the following capabilities are exposed:
• Counter increments every 30.5 microsecond
• Counter wraps in 2
32
-1 * 30.5 microsecond (~1.51 days)