Datasheet

Watchdog Timer
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
366 Document Number: 333577-002EN
19.3.1.3 Current Counter Value Register (WDT_CCVR)
MEM Offset (B0000000) 8h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_FFFFh
Bits Access
Type
Default Description PowerWell
31:0 RW 32'hFFFF Current Counter Value Register
(WDT_CCVR)
This register when read is the current value
of the internal counter
19.3.1.4 Current Restart Register (WDT_CRR)
MEM Offset (B0000000) 0Ch
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell
31:0 RW 32'h0 Current Restart Register (WDT_CRR)
This register is used to restart the WDT
counter. as a safetly feature to pervent
accidenctal restarts the value 0x76 must be
written. A restart also clears the WDT
interrupt. Reading this register returns zero
19.3.1.5 Interrupt Status Register (WDT_STAT)
MEM Offset (B0000000) 10h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell
31:1 RO 31'h0 Reserved (RSVD1)
Reserved
0 RO 1'h0 Interrupt Status Register (WDT_STAT)
Theis register shows the interrupt status of
the WDT 0 = interrupt is active 1 = interrupt
is inactive