Datasheet

Watchdog Timer
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 365
Bits Access
Type
Default Description PowerWell
Response mode 0 = Generate a system reset
1 = First generate interrupt if not cleared
generate reset
0 RW 1'h0 WDT Enable (WDT_ENABLE)
WDT Enable 0 = WDT Disable 1 = WDT
Enable
19.3.1.2 Timeout Range Register (WDT_TORR)
MEM Offset (B0000000) 4h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell
31:8 RO 24'h0 Reserved (RSVD1)
Reserved
7:4 RW 4'h0 Timeout period for initialization
(TOP_INIT)
Writes to these register bits have no effect
when the configuration parameter
WDT_HC_TOP = 1 or WDT_ALWAYS_EN = 1.
Used to select the timeout period that the
watchdog counter restarts from for the first
counter restart (kick). This register should be
written after reset and before the WDT is
enabled.
3:0 RW 4'h0 Timeout period (TOP)
Writes have no effect when the configuration
parameter WDT_HC_TOP = 1, thus
making this register read-only. This field is
used to select the timeout period from
which the watchdog counter restarts. A
change of the timeout period takes effect only
after the next counter restart (kick).