Datasheet

Watchdog Timer
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
364 Document Number: 333577-002EN
Table 48. Summary of WDT Registers—0xB0000000
MEM Address Default Instance Name Name
0x0 0000_0002h WDT_CR Control Register
0x4 0000_0000h WDT_TORR Timeout Range Register
0x8 0000_FFFFh WDT_CCVR Current Counter Value Register
0xC 0000_0000h WDT_CRR Current Restart Register
0x10 0000_0000h WDT_STAT Interrupt Status Register
0x14 0000_0000h WDT_EOI Interrupt Clear Register
0xE4 0000_0000h WDT_COMP_PARAM_5 Component Parameters
0xE8 0000_0000h WDT_COMP_PARAM_4 Component Parameters
0xEC 0000_0000h WDT_COMP_PARAM_3 Component Parameters
0xF0 0000_0000h WDT_COMP_PARAM_2 Component Parameters
0xF4 1000_0242h WDT_COMP_PARAM_1 Component Parameters Register 1
0xF8 3130_372Ah WDT_COMP_VERSION Component Version Register
0xFC 4457_0120h WDT_COMP_TYPE Component Type Register
19.3.1.1 Control Register (WDT_CR)
MEM Offset (B0000000) 0h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0002h
Bits Access
Type
Default Description PowerWell
31:6 RO 26'h0 Reserved (RSVD1)
Reserved
5 RW 1'h0 NO_NAME (NO_NAME)
Include for pin test purposes as it is the only
R/W register bit that is in every
configuratiopn of the Watchdog Controller.
4:2 RW 3'h0 Reset Pulse Width (RST_PULSE_WIDTH)
Rest pulse length 000 - 2 pclk cycles 001 - 4
pclk cycles 010 - 8 pclk cycles 011 - 16 pclk
cycles 100 - 32 pclk cycles 101 - 64 pclk
cycles 110 - 128 pclk cycles 111 - 256 pclk
cycles
1 RW 1'h1 RMOD (RMOD)