Datasheet

Watchdog Timer
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 363
7
2
23
262.144ms
8
2
24
524.288ms
9
2
25
1.049s
10
2
26
2.097s
11
2
27
4.194s
12
2
28
8.389s
13
2
29
16.777s
14
2
30
33.554s
15
2
31
67.109s
•
19.2 Use
When enabled the timer starts counting down from the programmed Timeout Value. If
the processor fails to reload the counter before it reaches zero (timeout) the WDT will
do one of two things depending on the programmed Response Mode:
Table 47. WDT Response Mode
Response
Mode
Behaviour
0
The WDT will request a SoC Warm Reset on a timeout.
1
The WDT will generate an Interrupt on first timeout.
If Interrupt has not been cleared by the second timeout
the WDT will then request a SoC Warm Reset.
See: Figure 54. WDT Behaviour for Response Mode of 1
NOTE: When the counter reaches zero it will wrap to the programmed Timeout Value and
continue decrementing.
Figure 15. WDT Behaviour for Response Mode of 1
The counter is reloaded by writing 76h to the Counter Restart Register, this will also
clear the WDT Interrupt.
The WDT Interrupt may also be cleared by reading the Interrupt Clear Register,
however this will not reload the counter.
19.3 Memory Mapped IO Registers
Registers listed are for the WDT, starting at base address B0000000h