Datasheet

Timers and PWM
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 355
18.4.1.4 Timer 1 End Of Interrupt (Timer1EOI)
MEM Offset (B0000800) 0B000080Ch
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bit
s
Acces
s Type
Defaul
t
Description PowerWel
l
ResetSigna
l
31:
1
RO 31'h0 Reserved (RSVD1)
Reserved
0 RO 1'h0 Timer End-of-Interrupt
(TIMER_END_OF_INTERRUP
T)
Reading from this register
returns b0, and clears the
interrupt form PWM/Timer.
18.4.1.5 Timer 1 Interrupt Status (Timer1IntStatus)
MEM Offset (B0000800) 0B0000810h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bit
s
Acces
s Type
Defaul
t
Description PowerWel
l
ResetSigna
l
31:
1
RO 31'h0 Reserved (RSVD1)
Reserved
0 RO 1'h0 Timer Interrupt Status
(TIMER_INTERRUPT_STATU
S)
A read of this register returns
the post masking interrupt
status of PWM/Timer.
If reading from this register
outside of an interrupt service
routine, software should first
perform 2 dummy writes to
another PWM/Timer register.