Datasheet

DMA Controller
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 333
Bits Access
Type
Default Description PowerWell ResetSignal
31:10 RO 22'b0 Reserved (RSV1)
9:8 WO 2'b0 Channel enable register
(CH_EN_WE)
7:2 RO 6'b0 Reserved (RSV0)
1:0 RW 2'b0 Channel enable register
(CH_EN)
Setting this bit enables a
channel. Clearing this bit
disables the channel.
0 = Disable the Channel
1 = Enable the Channel
The CH_EN_REG.CH_EN bit is
automatically cleared by
hardware to disable the
channel after the last AMBA
transfer of the DMA transfer
to the destination has
completed. Software can
therefore poll this bit to
determine when this channel
is free for a new DMA
transfer.
16.3.1.55 DMA ID (DMA_ID_REG)
Reads back the coreConsultant configured hardcoded ID number
MEM Offset (00000000) 0B07003A8h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:0 RO 32'b0 DMA ID (DMA_ID)
Hardcoded ID number