Datasheet

DMA Controller
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
332 Document Number: 333577-002EN
Bits Access
Type
Default Description PowerWell ResetSignal
7:2 RO 6'b0 Reserved (RSV0)
1:0 RW 2'b0 Destination Last
Transaction Request
register (LSTDST)
This bit is written only if the
corresponding channel write
enable bit in the Write Enable
field is asserted on the same
AHB write transfer, and if the
channel is enabled in the
CH_EN_REG register
16.3.1.53 DMA Configuration (DMA_CFG_REG)
Used to enable the DMA controller (DMAC), which must be done before any channel
activity can begin.
If the global channel enable bit is cleared while any channel is still active, then
DMA_EN still returns 1 to indicate that there are channels still active until hardware
has terminated all activity on all channels, at which point the DMA_EN bit returns 0
MEM Offset (00000000) 0B0700398h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:1 RO 31'b0 Reserved (RSV)
0 RW 1'b0 DMA global enable
(DMA_EN)
0 = disabled
1 = enabled
16.3.1.54 Channel Enable (CH_EN_REG)
Software can read this register in order to find out which channels are currently
inactive if needs to set up a new channel. It can then enable an inactive channel with
the required priority.
MEM Offset (00000000) 0B07003A0h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h