Datasheet

DMA Controller
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 331
16.3.1.51 Source Last Transaction Request (LST_SRC_REG)
MEM Offset (00000000) 0B0700388h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:10 RO 22'b0 Reserved (RSV1)
9:8 RW 2'b0 Source Last Transaction
Request write enable
(LSTSRC_WE)
0 = write disabled
1 = write enabled
7:2 RO 6'b0 Reserved (RSV0)
1:0 RW 2'b0 Source Last Transaction
Request register (LSTSRC)
This bit is written only if the
corresponding channel write
enable bit in the Write Enable
field is asserted on the same
AHB write transfer, and if the
channel is enabled in the
CH_EN_REG register
16.3.1.52 Destination Single Transaction Request
(LST_DST_REG)
MEM Offset (00000000) 0B0700390h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:10 RO 22'b0 Reserved (RSV1)
9:8 RW 2'b0 Destination Last
Transaction Request write
enable (LSTDST_WE)
0 = write disabled
1 = write enabled