Datasheet

DMA Controller
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
328 Document Number: 333577-002EN
16.3.1.47 Source Software Transaction Request
(REQ_SRC_REG)
MEM Offset (00000000) 0B0700368h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:10 RO 22'b0 Reserved (RSV1)
9:8 RW 2'b0 Source Software
Transaction Request write
enable (SRC_REQ_WE)
0 = write disabled
1 = write enabled
7:2 RO 6'b0 Reserved (RSV0)
1:0 RW 2'b0 Source Software
Transaction Request
register (SRC_REQ)
This bit is written only if the
corresponding channel write
enable bit in the Write Enable
field is asserted on the same
AHB write transfer, and if the
channel is enabled in the
CH_EN_REG register
16.3.1.48 Destination Software Transaction Request register
(REQ_DST_REG)
MEM Offset (00000000) 0B0700370h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:10 RO 22'b0 Reserved (RSV1)