Datasheet

DMA Controller
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
322 Document Number: 333577-002EN
16.3.1.39 Mask for IntSrcTran Interrupt (MASK_SRC_TRAN)
Source Transaction Complete Interrupt mask. The contents of the Raw Status register
is masked with the contents of the Mask register.
MEM Offset (00000000) 0B0700320h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Acces
s
Type
Defaul
t
Description PowerWe
ll
ResetSign
al
31:1
0
RO 22'b0 Reserved (RSV2)
9:8 RW 2'b0 Interrupt Mask Write Enable
(INT_MASK_WE)
0 = write disabled
1 = write enabled
7:2 RO 6'b0 Reserved (RSV1)
1:0 RW 2'b0 Mask for the interrupt
(INT_MASK)
Written only if the corresponding
mask write enable bit in the
INT_MASK_WE field is asserted
on the same AHB write transfer.
This allows software to set a
mask bit without performing a
read-modified write operation.
0 = masked
1 =
unmas
ked