Datasheet

DMA Controller
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 321
Bits Access
Type
Default Description PowerWell ResetSignal
Written only if the
corresponding mask write
enable bit in the
INT_MASK_WE field is
asserted on the same AHB
write transfer. This allows
software to set a mask bit
without performing a read-
modified write operation.
0 = masked
1 = unmasked
16.3.1.38 Mask for IntBlock Interrupt (MASK_BLOCK)
Block Transfer Complete Interrupt mask. The contents of the Raw Status register is
masked with the contents of the Mask register.
MEM Offset (00000000) 0B0700318h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:10 RO 22'b0 Reserved (RSV2)
9:8 RW 2'b0 Interrupt Mask Write
Enable (INT_MASK_WE)
0 = write disabled
1 = write enabled
7:2 RO 6'b0 Reserved (RSV1)
1:0 RW 2'b0 Mask for the interrupt
(INT_MASK)
Written only if the
corresponding mask write
enable bit in the
INT_MASK_WE field is
asserted on the same AHB
write transfer. This allows
software to set a mask bit
without performing a read-
modified write operation.
0 = masked
1 = unmasked