Datasheet

DMA Controller
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
320 Document Number: 333577-002EN
16.3.1.36 Status for IntErr Interrupt (STATUS_ERR)
Error Interrupt status
MEM Offset (00000000) 0B0700308h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:2 RO 30'b0 Reserved (RSV)
1:0 RO 2'b0 Status for IntErr Interrupt
(STATUS)
Stores all interrupt events
from channels after masking.
One bit allocated per channel.
Used to generate the DMAC
interrupt signals
16.3.1.37 Mask for IntTfr Interrupt (MASK_TFR)
DMA Transfer Complete Interrupt mask. The contents of the Raw Status register is
masked with the contents of the Mask register.
MEM Offset (00000000) 0B0700310h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:10 RO 22'b0 Reserved (RSV2)
9:8 RW 2'b0 Interrupt Mask Write
Enable (INT_MASK_WE)
0 = write disabled
1 = write enabled
7:2 RO 6'b0 Reserved (RSV1)
1:0 RW 2'b0 Mask for the interrupt
(INT_MASK)