Datasheet

DMA Controller
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 319
16.3.1.34 Status for IntSrcTran Interrupt
(STATUS_SRC_TRAN)
Source Transaction Complete Interrupt status
MEM Offset (00000000) 0B07002F8h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:2 RO 30'b0 Reserved (RSV)
1:0 RO 2'b0 Status for IntSrcTran
Interrupt (STATUS)
Stores all interrupt events
from channels after masking.
One bit allocated per channel.
Used to generate the DMAC
interrupt signals
16.3.1.35 Status for IntDstTran Interrupt
(STATUS_DST_TRAN)
Destination Transaction Complete Interrupt status
MEM Offset (00000000) 0B0700300h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:2 RO 30'b0 Reserved (RSV)
1:0 RO 2'b0 Status for IntDstTran
Interrupt (STATUS)
Stores all interrupt events
from channels after masking.
One bit allocated per channel.
Used to generate the DMAC
interrupt signals