Datasheet

DMA Controller
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
318 Document Number: 333577-002EN
16.3.1.32 Status for IntTfr Interrupt (STATUS_TFR)
DMA Transfer Complete Interrupt status
MEM Offset (00000000) 0B07002E8h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:2 RO 30'b0 Reserved (RSV)
1:0 RO 2'b0 Status for IntTfr Interrupt
(STATUS)
Stores all interrupt events
from channels after masking.
One bit allocated per channel.
Used to generate the DMAC
interrupt signals
16.3.1.33 Status for IntBlock Interrupt (STATUS_BLOCK)
Block Transfer Complete Interrupt status
MEM Offset (00000000) 0B07002F0h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:2 RO 30'b0 Reserved (RSV)
1:0 RO 2'b0 Status for IntBlock
Interrupt (STATUS)
Stores all interrupt events
from channels after masking.
One bit allocated per channel.
Used to generate the DMAC
interrupt signals