Datasheet

DMA Controller
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 317
Bits Access
Type
Default Description PowerWell ResetSignal
31:2 RO 30'b0 Reserved (RSV)
1:0 RW 2'b0 Raw Status for IntDstTran
Interrupt (RAW)
Interrupt events are stored in
this Raw Interrupt Status
register before masking. Each
bit in this register is cleared by
writing a 1 to the
corresponding location in the
correspondent Clear register
16.3.1.31 Raw Status for IntErr Interrupt (RAW_ERR)
Error Interrupt. This interrupt is generated when an ERROR response is received from
an AHB slave on the HRESP bus during a DMA transfer. In addition, the DMA transfer
is cancelled and the channel is disabled.
Peripheral controllers (SPI/I2C/UART) or memory controllers don?t generate error
response. Only AHB Fabric can generate error response if address points to a hole.
DMAC doesn't support slave AHB error response detection for Channel0 source and
Channel1 destination transfers, which is acceptable limitation as only AHB fabric can
generate error response and that too for address hole.
MEM Offset (00000000) 0B07002E0h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:2 RO 30'b0 Reserved (RSV)
1:0 RW 2'b0 Raw Status for IntErr
Interrupt (RAW)
Interrupt events are stored in
this Raw Interrupt Status
register before masking. Each
bit in this register is cleared by
writing a 1 to the
corresponding location in the
correspondent Clear register