Datasheet

DMA Controller
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
316 Document Number: 333577-002EN
16.3.1.29 Raw Status for IntSrcTran Interrupt
(RAW_SRC_TRAN)
Source Transaction Complete Interrupt. Generated after completion of the last AHB
transfer of the requested single/burst transaction from the handshaking interface
(either the hardware or software handshaking interface) on the source side. NOTE: If
the source is memory, then IntSrcTran interrupt should be ignored, as there is no
concept of a DMA transaction level for memory
MEM Offset (00000000) 0B07002D0h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:2 RO 30'b0 Reserved (RSV)
1:0 RW 2'b0 Raw Status for IntSrcTran
Interrupt (RAW)
Interrupt events are stored in
this Raw Interrupt Status
register before masking. Each
bit in this register is cleared by
writing a 1 to the
corresponding location in the
correspondent Clear register
16.3.1.30 Raw Status for IntDstTran Interrupt
(RAW_DST_TRAN)
Destination Transaction Complete Interrupt. Generated after completion of the last
AHB transfer of the requested single/burst transaction from the handshaking interface
(either the hardware or software handshaking interface) on the destination side.
NOTE: If the destination for a channel is memory, then that channel will never
generate the IntDstTran interrupt. Because of this, the corresponding bit in this field
will not be set.
MEM Offset (00000000) 0B07002D8h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h