Datasheet

DMA Controller
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 315
Bits Access
Type
Default Description PowerWell ResetSignal
31:2 RO 30'b0 Reserved (RSV)
1:0 RW 2'b0 Raw Status for IntTfr
Interrupt (RAW)
Interrupt events are stored in
this Raw Interrupt Status
register before masking. Each
bit in this register is cleared by
writing a 1 to the
corresponding location in the
correspondent Clear register
16.3.1.28 Raw Status for IntBlock Interrupt (RAW_BLOCK)
Block Transfer Complete Interrupt. This interrupt is generated on DMA block transfer
completion to the destination peripheral.
MEM Offset (00000000) 0B07002C8h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:2 RO 30'b0 Reserved (RSV)
1:0 RW 2'b0 Raw Status for IntBlock
Interrupt (RAW)
Interrupt events are stored in
this Raw Interrupt Status
register before masking. Each
bit in this register is cleared by
writing a 1 to the
corresponding location in the
correspondent Clear register