Datasheet

DMA Controller
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
314 Document Number: 333577-002EN
16.3.1.26 Channel1 Destination Scatter (DSR1)
The CTL0_L.DINC field controls whether the address increments or decrements. For a
fixed-address control, then the address remains constant throughout the transfer and
this register is ignored.
MEM Offset (00000000) 0B07000A8h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:25 RO 7'b0 Reserved (RSV)
24:20 RW 5'b0 Destination Scatter Count
(DSC)
Source contiguous transfer
count between successive
scatter boundaries. Specifies
the number of contiguous
destination transfers of
CTL0_L.DST_TR_WIDTH
between successive scatter
intervals. This is defined as a
scatter boundary
19:0 RW 20'b0 Destination Scatter
Interval (DSI)
Specifies the destination
address
increment/decrement in
multiples of
CTL0_L.DST_TR_WIDTH on a
scatter boundary when
scatter mode is enabled for
the destination transfer.
16.3.1.27 Raw Status for IntTfr Interrupt (RAW_TFR)
DMA Transfer Complete Interrupt. This interrupt is generated on DMA transfer
completion to the destination peripheral
MEM Offset (00000000) 0B07002C0h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h