Datasheet

DMA Controller
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
312 Document Number: 333577-002EN
Bits Access
Type
Default Description PowerWell ResetSignal
The AMBA Specification
recommends that the default
value of HPROT indicates a
non-cached, non-buffered,
privileged data access. The
reset value is used to indicate
such an access. HPROT[0] is
tied high because all
transfers are data accesses,
as there are no opcode
fetches. There is a one-to-
one mapping of these
register bits to the
HPROT[3:1] master interface
signals.
1 RW 1'b0 Channel FIFO mode
control (FIFO_MODE)
Determines how much space
or data needs to be available
in the FIFO before a burst
transaction request is
serviced.
0 = Space/data available for
single AHB transfer of the
specified transfer width.
1 = Data available is greater
than or equal to half the FIFO
depth for destination
transfers and space available
is greater than half the fifo
depth for source transfers.
The exceptions are at the end
of a burst transaction request
or at the end of a block
transfer.
0 RW 1'b0 Channel flow control mode
(FCMODE)
Determines when source
transaction requests are
serviced when the
Destination Peripheral is the
flow controller.
0 = Source transaction
requests are serviced when
they occur. Data pre-fetching
is enabled.
1 = Source transaction
requests are not serviced
until a
destination transaction
request occurs.