Datasheet

DMA Controller
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
308 Document Number: 333577-002EN
16.3.1.23 Channel1 Configuration LOWER (CFG_L1)
Contains fields that configure the DMA transfer. The channel configuration register
remains fixed for all blocks of a multi-block transfer. You need to program this register
prior to enabling the channel.
MEM Offset (00000000) 0B0700098h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0E00h
Bits Access
Type
Default Description PowerWell ResetSignal
31 RW 1'b0 Reload destination enable
(RELOAD_DST)
The DAR register can be
automatically reloaded from
its initial value at the end of
every block for multi-block
transfers. A new block
transfer is then initiated.
30 RW 1'b0 Reload source enable
(RELOAD_SRC)
The SAR register can be
automatically reloaded from
its initial value at the end of
every block for multi-block
transfers. A new block
transfer is then initiated.
29:20 RO 10'b0 Reserved (RSV2)
19 RW 1'b0 Source handshake polarity
(SRC_HS_POL)
0 = Active high
1 = Active low
Hardware handshake polarity
for Peripherals: 1. SPI =
Active high
2. I2C = Active high
3. UART A/B = Active low
18 RW 1'b0 Destination handshake
polarity (DST_HS_POL)
0 = Active high
1 = Active low
Hardware handshake polarity
for Peripherals: 1. SPI =
Active high
2. I2C = Active high
3. UART A/B = Active low