Datasheet

DMA Controller
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
304 Document Number: 333577-002EN
Bits Access
Type
Default Description PowerWell ResetSignal
3:1 RW 3'b000 Destination transfer width
(DST_TR_WIDTH)
Decoding for this field:
Value - Size(bits)
--------------------
000 - 8
001 - 16
010 - 32
011 - 64
100 - 128
101 - 256
11x - 256
0 RW 1'b1 Interrupt enable (INT_EN)
If set, then all interrupt-
generating sources are
enabled. Functions as a
global mask bit for all
interrupts for the channel.
RAW interrupt registers still
assert if INT_EN = 0.
16.3.1.18 Channel1 Control UPPER (CTL_U1)
Contains fields that control the DMA transfer.
It can be varied on a block-by-block basis within a DMA transfer when block chaining
is enabled. If status write-back is enabled, the content is written to the control
register location of the LLI in system memory at the end of the block transfer.
MEM Offset (00000000) 0B0700074h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0002h
Bits Acces
s
Type
Default Description PowerWe
ll
ResetSign
al
31:1
3
RO 19'b0 Reserved (RSV1)
12 RW 1'b0 Done bit (DONE)
If status write-back is
enabled, the upper
word of the control
register,
CTL0_U[31:0], is
written to the control
register location of the
Linked