Datasheet

DMA Controller
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
300 Document Number: 333577-002EN
16.3.1.17 Channel1 Control LOWER (CTL_L1)
Contains fields that control the DMA transfer
It is part of the block descriptor (linked list item - LLI) when block chaining is enabled.
It can be varied on a block-by-block basis within a DMA transfer when block chaining
is enabled.
MEM Offset (00000000) 0B0700070h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0030_4801h
Bits Access
Type
Default Description PowerWell ResetSignal
31:29 RO 3'b0 Reserved (RSV2)
28 RW 1'b0 LLP_SRC_EN
(LLP_SRC_EN)
Block chaining is enabled on
the source side only if the
LLP_SRC_EN field is high and
LLPx.LOC is non-zero
27 RW 1'b0 LLP_DST_EN
(LLP_DST_EN)
Block chaining is enabled on
the destination side only if
the
LLP_DST_EN field is high and
LLP0.LOC is non-zero
26:25 RO 2'b0 Source AMBA Layer (SMS)
Hardcoded the Master
interface attached to the
source of channel 0.
24:23 RO 2'b0 Destination AMBA Layer
(DMS)
Hardcoded the Master
interface attached to the
destination of channel 0
22:20 RW 3'b011 Transfer Type and Flow
Control (TT_FC)
The following transfer types
are supported:
Code - Type - Flow Controller
---------------------------------
-----------------
000 - Memory to Memory -
DMAC
---------------------------------