Datasheet
Ballout and Package Information
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
30 Document Number: 333577-002EN
3.3 Pin Multiplexing
There are 15 dedicated pins + 1 QFN GND plane and 25 functional pins which can be
configured as GPIO (GPIO[24:0]) or other functions (I2C/UART/SPI/JTAG). There are
two major IO modes: user mode and test mode. In user mode, each pin can be
individually configured in one of the 4 user modes (FUNC 0/1/2/3). By default, after
power-on-reset (RST_N) or cold reset, SoC comes up in user mode 0 function
(FUNC0). SOC firmware/software is responsible for enabling the platform specific
configuration by programming the respective IO pad control registers.
Out of 25 functional pins, 19 pins are double bonded to Analog input pads and digital
pads while 6 pins are digital only pads. All analog pads (AI[18:0]) are specified with
respect to AVDD and all digital pads are with respect to IOVDD. The analog inputs (AI)
are connected to ADC or Comparators inside the SoC. AI[5:0] is connected to fast
response/high performance comparator / fast channel of ADC; and AI[18:6] are
connected to slow response/low power comparator / slow channel of ADC. Any wake
capable analog inputs shall be connected only to any of AI[18:6] and not to AI[5:0].
Table 3. Pin Multiplexing
Pin
Num
ber
Pin/Ball
Name Type
Volta
ge
Function
0
Function
1
Function
2 Function 3
VSS
GND
PWR
0 V
GND
GND
GND
GND
27
PVDD
PWR
PVDD
PVDD
PVDD
PVDD
PVDD
40
AVDD
PWR
PVDD
AVDD
AVDD
AVDD
AVDD
12
IOVDD
PWR
PVDD
IOVDD
IOVDD
IOVDD
IOVDD
28
VSENSE
PWR
DVDD
VSENSE
VSENSE
VSENSE
VSENSE
25
GSENSE
PWR
0 V
GSENSE
GSENSE
GSENSE
GSENSE
26
LX
PWR
DVDD
LX
LX
LX
LX
29
VREN
PWR
PVDD
VREN
VREN
VREN
VREN
17
DVDD
PWR
DVDD
DVDD
DVDD
DVDD
DVDD
30
RST_N
RST
PVDD
RST_N
RST_N
RST_N
RST_N
22
RTC_XTALI
CLK
DVDD
RTC_XTALI
RTC_XTALI
RTC_XTALI
RTC_XTALI
23
RTC_XTALO
CLK
DVDD
RTC_XTALO
RTC_XTALO
RTC_XTALO
RTC_XTALO
19
HYB_XTALI
CLK
DVDD
HYB_XTALI
HYB_XTALI
HYB_XTALI
HYB_XTALI
20
HYB_XTALO
CLK
DVDD
HYB_XTALO
HYB_XTALO
HYB_XTALO
HYB_XTALO
1
AR
PWR
AVDD
AR
AR
AR
AR
31
F_0
GPIO
IOVDD/
AVDD
GPIO0
AI0
SPI_M_SS0
32
F_1
GPIO
IOVDD/
AVDD
GPIO1
AI1
SPI_M_SS1
33
F_2
GPIO
IOVDD/
AVDD
GPIO2
AI2
SPI_M_SS2
34
F_3
GPIO
IOVDD/
AVDD
GPIO3
AI3
SPI_M_SS3