Datasheet

DMA Controller
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 299
Bits Access
Type
Default Description PowerWell ResetSignal
Updated after each destination
transfer. The DINC field in the
CTL0_L register determines
whether the address
increments, decrements, or is
left unchanged on every
destination transfer
throughout the block transfer.
16.3.1.16 Channel1 Linked List Pointer (LLP1)
Program this register to point to the first Linked List Item (LLI) in memory prior to
enabling the channel if block chaining is enabled
MEM Offset (00000000) 0B0700068h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:2 RW 30'b0 Starting Address In
Memory (LOC)
Starting Address In Memory of
next LLI if block chaining is
enabled.
Note that the two LSBs of the
starting address are not stored
because the address is
assumed to be aligned to a
32-bit boundary.
LLI accesses are always 32-bit
accesses (Hsize = 2) aligned
to 32-bit boundaries and
cannot be changed or
programmed to anything other
than 32-bit.
1:0 RO 2'b0 Reserved (RSV)