Datasheet

DMA Controller
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
296 Document Number: 333577-002EN
Bits Access
Type
Default Description PowerWell ResetSignal
Determines when source
transaction requests are
serviced when the
Destination Peripheral is the
flow controller.
0 = Source transaction
requests are serviced when
they occur. Data pre-fetching
is enabled.
1 = Source transaction
requests are not serviced
until a
destination transaction
request occurs.
In this mode, the amount of
data transferred from the
source is limited so that it is
guaranteed to be transferred
to the destination prior to
block termination by the
destination. Data pre-
fetching is disabled.
16.3.1.12 Channel0 Source Gather (SGR0)
The CTL0_L.SINC field controls whether the address increments or decrements. For a
fixed-address control, then the address remains constant throughout the transfer and
this register is ignored.
MEM Offset (00000000) 0B0700048h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:25 RO 7'b0 Reserved (RSV)
24:20 RW 5'b0 Source Gather Count
(SGC)
Source contiguous transfer
count between successive
gather boundaries. Specifies
the number of contiguous
source transfers of
CTL0_L.SRC_TR_WIDTH
between successive gather
intervals. This is defined as a
gather boundary