Datasheet

DMA Controller
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 293
Bits Access
Type
Default Description PowerWell ResetSignal
0 = Not suspended.
1 = Suspend DMA transfer
from the source.
7:5 RW 3'b0 Channel Priority
(CH_PRIOR)
Priority value equal to 7 is
the highest priority, and 0 is
the lowest. This field must be
programmed within the
following range: 0: 1
A programmed value outside
this range will cause
erroneous behavior.
4:0 RO 5'b0 Reserved (RSV0)
16.3.1.11 Channel0 configuration UPPER (CFG_U0)
Contains fields that configure the DMA transfer. The channel configuration register
remains fixed for all blocks of a multi-block transfer. You need to program this register
prior to enabling the channel.
MEM Offset (00000000) 0B0700044h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0004h
Bits Access
Type
Default Description PowerWell ResetSignal
31:15 RO 17'h0 Reserved (RSV5)
14:11 RW 4'h0 Destination hardware
interface (DEST_PER)