Datasheet

DMA Controller
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
290 Document Number: 333577-002EN
16.3.1.8 Channel0 Source Status Address (SSTATAR0)
After the completion of each block transfer, hardware can retrieve the source status
information from the address pointed to by the contents of this register
MEM Offset (00000000) 0B0700030h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:0 RW 32'b0 Channel Source Status
Address (SSTATAR)
Pointer from where hardware
can fetch the source status
information, which is
registered in the SSTAT0
register and written out to the
SSTAT0 register location of the
LLI before the start of the next
block.
16.3.1.9 Channel0 Destination Status Address (DSTATAR0)
After the completion of each block transfer, hardware can retrieve the destination
status information from the address pointed to by the contents of this register
MEM Offset (00000000) 0B0700038h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:0 RW 32'b0 Channel Destination Status
Address (DSTATAR)
Pointer from where hardware
can fetch the destination
status information, which is
registered in the DSTAT0
register and written out to the
DSTAT0 register location of
the LLI before the start of the
next block.