Datasheet

DMA Controller
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 289
16.3.1.6 Channel0 Source Status (SSTAT0)
This register is a temporary placeholder for the source status information on its way to
the SSTAT0 register location of the LLI. The source status information should be
retrieved by software from the SSTAT0 register location of the LLI, and not by a read
of this register over the DMAC slave interface.
MEM Offset (00000000) 0B0700020h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:0 RW 32'b0 Channel Source Status
(SSTAT)
Source status information
retrieved by hardware from
the address pointed to by the
contents of the SSTATAR0
register.
16.3.1.7 Channel0 Destination Status (DSTAT0)
This register is a temporary placeholder for the destination status information on its
way to the DSTAT0 register location of the LLI. The destination status information
should be retrieved by software from the DSTAT0 register location of the LLI and not
by a read of this register over the DMAC slave interface
MEM Offset (00000000) 0B0700028h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:0 RW 32'b0 Channel Destination Status
(DSTAT)
Destination status information
retrieved by hardware from
the address pointed to by the
contents of the DSTATAR0
register