Datasheet

DMA Controller
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
282 Document Number: 333577-002EN
Updated after each destination
transfer. The DINC field in the
CTL0_L register determines
whether the address
increments, decrements, or is
left unchanged on every
destination transfer
throughout the block transfer.
16.3.1.3 Channel0 Linked List Pointer (LLP0)
Program this register to point to the first Linked List Item (LLI) in memory prior to
enabling the channel if block chaining is enabled
MEM Offset (00000000) 0B0700010h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:2 RW 30'b0 Starting Address In
Memory (LOC)
Starting Address In Memory of
next LLI if block chaining is
enabled.
Note that the two LSBs of the
starting address are not stored
because the address is
assumed to be aligned to a
32-bit boundary.
LLI accesses are always 32-bit
accesses (Hsize = 2) aligned
to 32-bit boundaries and
cannot be changed or
programmed to anything other
than 32-bit.
1:0 RO 2'b0 Reserved (RSV)
16.3.1.4 Channel0 Control LOWER (CTL_L0)
Contains fields that control the DMA transfer
It is part of the block descriptor (linked list item - LLI) when block chaining is enabled.
It can be varied on a block-by-block basis within a DMA transfer when block chaining
is enabled.
MEM Offset (00000000) 0B0700018h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0030_4801h