Datasheet

DMA Controller
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 281
16.3.1.1 Channel0 Source Address (SAR0)
Source Address of DMA transfer
The starting source address is programmed by software before the DMA channel is
enabled, or by an LLI update before the start of the DMA transfer.
While the DMA transfer is in progress, this register is updated to reflect the source
address of the current transfer.
MEM Offset (00000000) 0B0700000h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:0 RW 32'b0 Current Source Address of
DMA transfer (SAR)
Updated after each source
transfer. The SINC field in the
CTL0_L register determines
whether the address
increments, decrements, or is
left unchanged on every
source transfer throughout the
block transfer.
16.3.1.2 Channel0 Destination Address (DAR0)
Destination address of DMA transfer
The starting destination address is programmed by software before the DMA channel
is enabled, or by an LLI update before the start of the DMA transfer. While the DMA
transfer is in progress, this register is updated to reflect the destination address of the
current transfer.
MEM Offset (00000000) 0B0700008h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:0 RW 32'b0 Current Destination
address of DMA transfer
(DAR)