Datasheet

DMA Controller
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 279
In the event on an ERROR response the DMA transfer is cancelled and the
corresponding channel is disabled, an Error Response interrupt will be generated if the
channel configured to do so.
16.3 Memory Mapped IO Registers
Registers listed are for the DMA Controller, starting at base address B0700000h.
MEM
Address
Default Instance Name Name
0xB0700000 0000_0000h SAR0 Channel0 Source Address
0xB0700008 0000_0000h DAR0 Channel0 Destination Address
0xB0700010 0000_0000h LLP0 Channel0 Linked List Pointer
0xB0700018 0030_4801h CTL_L0 Channel0 Control LOWER
0xB070001C 0000_0002h CTL_U0 Channel0 Control UPPER
0xB0700020 0000_0000h SSTAT0 Channel0 Source Status
0xB0700028 0000_0000h DSTAT0 Channel0 Destination Status
0xB0700030 0000_0000h SSTATAR0 Channel0 Source Status Address
0xB0700038 0000_0000h DSTATAR0 Channel0 Destination Status Address
0xB0700040 0000_0E00h CFG_L0 Channel0 Configuration LOWER
0xB0700044 0000_0004h CFG_U0 Channel0 configuration UPPER
0xB0700048 0000_0000h SGR0 Channel0 Source Gather
0xB0700050 0000_0000h DSR0 Channel0 Destination Scatter
0xB0700058 0000_0000h SAR1 Channel1 Source Address
0xB0700060 0000_0000h DAR1 Channel1 Destination Address
0xB0700068 0000_0000h LLP1 Channel1 Linked List Pointer
0xB0700070 0030_4801h CTL_L1 Channel1 Control LOWER
0xB0700074 0000_0002h CTL_U1 Channel1 Control UPPER
0xB0700078 0000_0000h SSTAT1 Channel1 Source Status
0xB0700080 0000_0000h DSTAT1 Channel1 Destination Status
0xB0700088 0000_0000h SSTATAR1 Channel1 Source Status Address
0xB0700090 0000_0000h DSTATAR1 Channel1 Destination Status Address
0xB0700098 0000_0E00h CFG_L1 Channel1 Configuration LOWER
0xB070009C 0000_0004h CFG_U1 Channel1 configuration UPPER
0xB07000A0 0000_0000h SGR1 Channel1 Source Gather
0xB07000A8 0000_0000h DSR1 Channel1 Destination Scatter
0xB07002C0 0000_0000h RAW_TFR Raw Status for IntTfr Interrupt
0xB07002C8 0000_0000h RAW_BLOCK Raw Status for IntBlock Interrupt
0xB07002D0 0000_0000h RAW_SRC_TRAN Raw Status for IntSrcTran Interrupt