Datasheet

DMA Controller
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
278 Document Number: 333577-002EN
Interface ID Peripheral
10 Reserved
11 Reserved
12 I2C Master 0 TX
13 I2C Master 0 RX
14 Reserved
15 Reserved
Transfer Type and Flow Control are configurable on a per Channel basis, the following
Flow Control options are available depending on the Transfer Type:
Table 39. Transfer Type and Flow Control Options
Transfer Type Supported Flow Control Agent(s)
Memory to Memory DMA Controller
Peripheral to Memory DMA Controller or
Peripheral
Memory to Peripheral DMA Controller or
Peripheral
Peripheral to Peripheral DMA Controller or
Source Peripheral or
Destination Peripheral
Multi-Block Transfers are achieved through:
• Linked List (Block Chaining)
• Address Auto-Reloading
• Contiguous Addressing
There are 5 possible sources for Channel Interrupts, each of these sources can be
individually masked. The sources are provided in the following list:
1. DMA Transfer Complete - generated on DMA transfer completion to the
Destination Peripheral.
2. Block Transfer Complete - generated on DMA block transfer completion to the
Destination Peripheral.
3. Source Transaction Complete - generated after completion of the last AHB
transfer of the requested single/burst transaction from the handshaking
interface (either the hardware or software handshaking interface) on the
source side.
4. Destination Transaction Complete - generated after completion of the last AHB
transfer of the requested single/burst transaction from the handshaking
interface (either the hardware or software handshaking interface) on the
destination side.
5. Error Response – generated when an ERROR response is received from an
AHB slave on the HRESP bus during a DMA transfer.