Datasheet

DMA Controller
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 277
16 DMA Controller
The SoC contains a single 2-Channel DMA controller. The DMA controller supports
Single or Multi-Block transfers from Memory to Memory, Peripheral to Memory,
Memory to Peripheral or Peripheral to Peripheral.
16.1 Features
The following is a list of the DMA Controller features:
• 2 Unidirectional Channels
• Configurable Channel Prioritization
• Software Handshaking
• Hardware Handshaking Interfaces
• Configurable Transfer Type and Flow Control
• Supports Single-Block Transfers
• Supports Multi-Block Transfers
• Scatter-Gather
• Interrupt Generation per Channel:
o DMA Transfer Complete
o Block Transfer Complete
o Source Transaction Complete
o Destination Transaction Complete
o Error Response
16.2 Use
DMA Transfers are initiated either through Software or Hardware Handshaking
Interfaces. The Handshaking Interface is configurable on a per Channel basis. The
following Hardware Handshaking Interfaces are available for selection:
Table 38. Hardware Handshake Interfaces
Interface ID Peripheral
0 UART 0 TX
1 UART 0 RX
2 UART 1 TX
3 UART 1 RX
4 SPI Master 0 TX
5 SPI Master 0 RX
6 Reserved
7 Reserved
8 SPI Slave TX
9 SPI Slave RX