Datasheet

SPI
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
276 Document Number: 333577-002EN
Bits Access
Type
Default Description PowerWell ResetSignal
31:16 RO 16'b0 Reserved 1 (RSVD1)
Reserved
15:0 RW 16'h0 Data Register (DR)
When writing to this register,
you must right-justify the
data. Read
data are automatically right-
justified.
Read = Receive FIFO buffer
Write = Transmit FIFO buffer
15.3.1.61 RX Sample Delay Register (RX_SAMPLE_DLY)
This register controls the number of ssi_clk cycles that are delayed,from the default
sample time,before the actual sample of the rxd input signal occurs. It is impossible to
write to this register when the SPI Controller is enabled; the SPI Controller is enabled
and disabled by writing to the SSIENR register.
MEM Offset (B0001000) F0h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:4 RO 28'h0 Reserved 1 (RSVD1)
Reserved
3:0 RW/L 4'h0 Receive Data Sample Delay
(RSD)
This register is used to delay
the sample of the rxd input
signal. Each value represents
a single ssi_clk delay on the
sample of the rxd signal.
NOTE: If this register is
programmed with a value that
exceeds the depth of the
internal shift registers
(SSI_RX_DLY_SR_DEPTH