Datasheet

SPI
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
266 Document Number: 333577-002EN
Bits Access
Type
Default Description PowerWell ResetSignal
31:16 RO 16'b0 Reserved 1 (RSVD1)
Reserved
15:0 RW 16'h0 Data Register (DR)
When writing to this register,
you must right-justify the
data. Read
data are automatically right-
justified.
Read = Receive FIFO buffer
Write = Transmit FIFO buffer
15.3.1.46 Data Register (DR21)
The SPI Controller data register is a 16-bit read/write buffer for the transmit/receive
FIFOs. When the register is read, data in the receive FIFO buffer is accessed. When it
is written to, data are moved into the transmit FIFO buffer; a write can occur only
when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
NOTE : The DR register in the SPI Controller occupies thirty-six 32-bit address
locations of the memory map to facilitate AHB burst transfers. Writing to any of these
address locations has the same effect as pushing the data from the pwdata bus into
the transmit FIFO. Reading from any of these locations has the same effect as popping
data from the receive FIFO onto the prdata bus. The FIFO buffers on the SPI
Controller are not addressable.
MEM Offset (B0001000) B4h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:16 RO 16'b0 Reserved 1 (RSVD1)
Reserved
15:0 RW 16'h0 Data Register (DR)
When writing to this register,
you must right-justify the
data. Read
data are automatically right-
justified.
Read = Receive FIFO buffer
Write = Transmit FIFO buffer