Datasheet

SPI
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
250 Document Number: 333577-002EN
15.3.1.21 DMA Transmit Data Level (DMATDLR)
MEM Offset (B0001000) 50h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:3 RO 29'h0 Reserved 1 (RSVD1)
Reserved
2:0 RW 3'h0 DMA Transmit Data Level
(DMATDL)
Transmit Data Level. This bit
field controls the level at
which a DMA request is made
by the transmit logic. It is
equal to the watermark level;
that is, the dma_tx_req signal
is generated when the number
of valid data entries in the
transmit FIFO is equal to or
below this field value, and
TDMAE = 1.
15.3.1.22 DMA Receive Data Level (DMARDLR)
MEM Offset (B0001000) 54h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:3 RO 29'b0 Reserved 1 (RSVD1)
Reserved
2:0 RW 3'h0 Receive Data Level
(DMARDL)
This bit field controls the level
at which a DMA request is
made by the receive logic. The
watermark level =
DMARDL+1; that is,
dma_rx_req is generated
when the number of valid data
entries in the receive FIFO is
equal to or above this field
value + 1, and RDMAE=1.