Datasheet

SPI
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 249
15.3.1.19 Interrupt Clear Register (ICR)
MEM Offset (B0001000) 48h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:1 RO 31'b0 Reserved 1 (RSVD1)
Reserved
0 RO/C 1'h0 Interrupt Clear Register
(ICR)
This register is set if any of
the interrupts below are
active. A read clears the
ssi_txo_intr, ssi_rxu_intr,
ssi_rxo_intr, and the
ssi_mst_intr interrupts.
Writing to this register has no
effect.
15.3.1.20 DMA Control Register (DMACR)
The register is used to enable the DMA Controller interface operation.
MEM Offset (B0001000) 4Ch
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:2 RO 30'h0 Reserved 1 (RSVD1)
Reserved
1 RW 1'h0 Transmit DMA Enable
(TDMAE)
This bit enables/disables the
transmit FIFO DMA channel.
0 = Transmit DMA disabled
1 = Transmit DMA enabled
0 RW 1'h0 Receive DMA Enable
(RDMAE)
This bit enables/disables the
receive FIFO DMA channel.
0 = Receive DMA disabled
1 = Receive DMA enabled