Datasheet

SPI
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
248 Document Number: 333577-002EN
15.3.1.17 Receive FIFO Underflow Interrupt Clear Register
(RXUICR)
MEM Offset (B0001000) 40h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:1 RO 31'h0 Reserved 1 (RSVD1)
Reserved
0 RO/C 1'h0 Clear Receive FIFO
Underflow Interrupt
(RXUICR)
This register reflects the status
of the interrupt. A read from
this register clears the
ssi_rxu_intr interrupt; writing
has no effect.
15.3.1.18 Multi-Master Interrupt Clear Register (MSTICR)
MEM Offset (B0001000) 44h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:1 RO 31'b0 Reserved 1 (RSVD1)
Reserved
0 RO 1'h0 RSVD (RSVD)
Reserved