Datasheet

SPI
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 247
15.3.1.15 Transmit FIFO Overflow Interrupt Clear Register
(TXOICR)
MEM Offset (B0001000) 38h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:1 RO 31'b0 Reserved 1 (RSVD1)
Reserved
0 RO/C 1'h0 Clear Transmit FIFO
Overflow Interrupt
(TXOICR)
This register reflects the status
of the interrupt. A read from
this register clears the
ssi_txo_intr interrupt; writing
has no effect.
15.3.1.16 Receive FIFO Overflow Interrupt Clear Register
(RXOICR)
MEM Offset (B0001000) 3Ch
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:1 RO/C 31'b0 Reserved 1 (RSVD1)
Reserved
0 RO/C 1'h0 Clear Receive FIFO
Overflow Interrupt
(RXOICR)
This register reflects the status
of the interrupt. A read from
this register clears the
ssi_rxo_intr interrupt; writing
has no effect.