Datasheet

SPI
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
246 Document Number: 333577-002EN
15.3.1.14 Raw Interrupt Status Register (RISR)
This register reports the status of the SPI Controller interrupts prior to masking
MEM Offset (B0001000) 34h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:6 RO 26'b0 Reserved 1 (RSVD1)
Reserved
5 RO 1'h0 RSVD (RSVD)
Reserved
4 RO 1'h0 Receive FIFO Full Raw
Interrupt Status (RXFIR)
0 : ssi_rxf_intr interrupt is not
active prior masking
1 : ssi_rxf_intr interrupt is
active prior masking
3 RO 1'h0 Receive FIFO Overflow Raw
Interrupt Status (RXOIR)
0 : ssi_rxo_intr interrupt is
active prior masking
1 : ssi_rxo_intr interrupt is not
active prior masking
2 RO 1'h0 Receive FIFO Underflow
Raw Interrupt Status
(RXUIR)
0 : ssi_rxu_intr interrupt is not
active prior masking
1 : ssi_rxu_intr interrupt is
active prior masking
1 RO 1'h0 Transmit FIFO Overflow
Raw Interrupt Status
(TXOIR)
0 : ssi_txo_intr interrupt is not
active prior masking 1 :
ssi_txo_intr interrupt is active
prior masking
0 RO 1'h0 Transmit FIFO Empty Raw
Interrupt Status (TXEIR)
0 : ssi_txe_intr interrupt is not
active prior masking
1 : ssi_txe_intr interrupt is
active prior masking