Datasheet

SPI
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 245
15.3.1.13 Interrupt Status Register (ISR)
This register reports the status of the SPI Controller interrupts after they have been
masked.
MEM Offset (B0001000) 30h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:6 RO 26'b0 Reserved 1 (RSVD1)
Reserved
5 RO 1'h0 RSVD (RSVD)
Reserved
4 RO 1'h0 Receive FIFO Full Interrupt
Status (RXFIS)
0 : ssi_rxf_intr interrupt is not
active after masking
1 : ssi_rxf_intr interrupt is
active after masking
3 RO 1'h0 Receive FIFO Overflow
Interrupt Status (RXOIS)
0 : ssi_rxo_intr interrupt is
active after masking
1 : ssi_rxo_intr interrupt is not
active after masking
2 RO 1'h0 Receive FIFO Underflow
Interrupt Status (RXUIS)
0 : ssi_rxu_intr interrupt is not
active after masking
1 : ssi_rxu_intr interrupt is
active after masking
1 RO 1'h0 Transmit FIFO Overflow
Interrupt Status (TXOIS)
0 : ssi_txo_intr interrupt is not
active after masking 1 :
ssi_txo_intr interrupt is active
after masking
0 RO 1'h0 Transmit FIFO Empty
Interrupt Status (TXEIS)
0 : ssi_txe_intr interrupt is not
active after masking
1 : ssi_txe_intr interrupt is
active after masking