Datasheet

SPI
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
244 Document Number: 333577-002EN
15.3.1.12 Interrupt Mask Register (IMR)
This read/write register masks or enables all interrupts generated by the SPI
Controller.
MEM Offset (B0001000) 2Ch
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_003Fh
Bits Access
Type
Default Description PowerWell ResetSignal
31:6 RO 26'b0 Reserved 1 (RSVD1)
Reserved
5 RO 1'h1 RSVD (RSVD)
Reserved
4 RW 1'h1 Receive FIFO Full Interrupt
Mask (RXFIM)
0 : ssi_rxf_intr interrupt is
masked
1 : ssi_rxf_intr interrupt is not
masked
3 RW 1'h1 Receive FIFO Overflow
Interrupt Mask (RXOIM)
0 : ssi_rxo_intr interrupt is
masked
1 : ssi_rxo_intr interrupt is not
masked
2 RW 1'h1 Receive FIFO Underflow
Interrupt Mask (RXUIM)
0 : ssi_rxu_intr interrupt is
masked
1 : ssi_rxu_intr interrupt is not
masked
1 RW 1'h1 Transmit FIFO Overflow
Interrupt Mask (TXOIM)
0 : ssi_txo_intr interrupt is
masked 1 : ssi_txo_intr
interrupt is not masked
0 RW 1'h1 Transmit FIFO Empty
Interrupt Mask (TXEIM)
0 : ssi_txe_intr interrupt is
masked
1 : ssi_txe_intr interrupt is not
masked