Datasheet

SPI
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 243
Bits Access
Type
Default Description PowerWell ResetSignal
4 RO 1'h0 Receive FIFO Full (RFF)
When the receive FIFO is
completely full, this bit is set.
When the receive FIFO
contains one or more empty
location, this bit is cleared.
0 : Receive FIFO is not full
1 : Receive FIFO is full
3 RO 1'h0 Receive FIFO Not Empty
(RFNE)
Set when the receive FIFO
contains one or more entries
and is cleared when the
receive FIFO is empty. This bit
can be polled by software to
completely empty the receive
FIFO.
0 : Receive FIFO is empty
1 : Receive FIFO is not empty
2 RO 1'h1 Transmit FIFO Empty (TFE)
When the transmit FIFO is
completely empty, this bit is
set. When the transmit FIFO
contains one or more valid
entries, this bit is cleared. This
bit field does not request an
interrupt.
0 : Transmit FIFO is not empty
1 : Transmit FIFO is empty
1 RO 1'h1 Transmit FIFO Not Full
(TFNF)
Set when the transmit FIFO
contains one or more empty
locations, and is cleared when
the FIFO is full.
0 : Transmit FIFO is full
1 : Transmit FIFO is not full
0 RO 1'h0 SSI Busy Flag (BUSY)
When set, indicates that a
serial transfer is in progress;
when cleared indicates that
the SPI Controller is idle or
disabled.
0 : SPI Controller is idle or
disabled
1 : SPI Controller is actively
transferring data