Datasheet

SPI
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
242 Document Number: 333577-002EN
15.3.1.10 Receive FIFO Level Register (RXFLR)
MEM Offset (B0001000) 24h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:4 RO 28'b0 Reserved 1 (RSVD1)
Reserved
3:0 RO 4'h0 Receive FIFO Level
(RXFLR)
Contains the number of valid
data entries in the receive
FIFO.
15.3.1.11 Status Register (SR)
This is a read-only register used to indicate the current transfer status, FIFO status,
and any transmission/reception errors that may have occurred. The status register
may be read at any time. None of the bits in this register request an interrupt.
MEM Offset (B0001000) 28h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0006h
Bits Access
Type
Default Description PowerWell ResetSignal
31:7 RO 25'h0 Reserved 1 (RSVD1)
Reserved
6 RO 1'h0 RSVD (RSVD)
Reserved
5 RO 1'h0 Transmission Error (TXE)
Set if the transmit FIFO is
empty when a transfer is
started. This bit can be set
only when the SPI Controller is
configured as a slave device.
Data from the previous
transmission is resent on the
txd line. This bit is cleared
when read.
0 : No error
1 : Transmission error