Datasheet

SPI
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 241
Bits Access
Type
Default Description PowerWell ResetSignal
2:0 RW 3'h0 Receive FIFO Threshold
(RFT)
Controls the level of entries
(or above) at which the
receive FIFO controller triggers
an interrupt. If you attempt to
set this value greater than the
depth of the FIFO, this field is
not written and retains its
current value. When the
number of receive FIFO entries
is greater than or equal to this
value + 1, the receive FIFO
full interrupt is triggered.
15.3.1.9 Transmit FIFO Level Register (TXFLR)
MEM Offset (B0001000) 20h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:4 RO 28'b0 Reserved 1 (RSVD1)
Reserved
3:0 RO 4'h0 Transmit FIFO Level
(TXTFL)
Contains the number of valid
data entries in the transmit
FIFO.