Datasheet

SPI
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
240 Document Number: 333577-002EN
15.3.1.7 Transmit FIFO Threshold Level (TXFTLR)
This register controls the threshold value for the transmit FIFO memory. The SPI
Controller is enabled and disabled by writing to the SSIENR register.
MEM Offset (B0001000) 18h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:3 RO 29'b0 Reserved 1 (RSVD1)
Reserved
2:0 RW 3'b0 Transmit FIFO Threshold
(TXFTLR)
Controls the level of entries
(or below) at which the
transmit FIFO controller
triggers an interrupt. If you
attempt to set register field to
a value greater than or equal
to the depth of the FIFO, this
field is not written and retains
its current value. When the
number of transmit FIFO
entries is less than or equal to
this value, the transmit FIFO
empty interrupt is triggered.
15.3.1.8 Receive FIFO Threshold Level (RXFTLR)
This register controls the threshold value for the receive FIFO memory. The SPI
Controller is enabled and disabled by writing to the SSIENR register.
MEM Offset (B0001000) 1Ch
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:3 RO 29'b0 Reserved 1 (RSVD1)
Reserved