Datasheet

SPI
Intel
®
Quark™ microcontroller D2000
January 2016 Datasheet
Document Number: 333577-002EN 239
15.3.1.6 Baud Rate Select (BAUDR)
This register is valid only when the SPI Controller is configured as a master device.
When the SPI Controller is configured as a serial slave, writing to this location has no
effect; reading from this location returns 0. The register derives the frequency of the
serial clock that regulates the data transfer. The 16-bit field in this register defines the
ssi_clk divider value. It is impossible to write to this register when the SPI Controller
is enabled. The SPI Controller is enabled and disabled by writing to the SSIENR
register.
MEM Offset (B0001000) 14h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:16 RO 16'b0 Reserved 1 (RSVD1)
Reserved
15:0 RW/L 16'h0 SSI Clock Divider (SCKDV)
The LSB for this field is
always set to 0 and is
unaffected by a write
operation, which ensures an
even value is held in this
register. If the value is 0, the
serial output clock (sclk_out)
is disabled. The frequency of
the sclk_out is derived from
the following equation:
Fsclk_out = Fssi_clk/SCKDV
where SCKDV is any even
value between 2 and 65534.
For example:
for Fssi_clk = 3.6864MHz and
SCKDV =2
Fsclk_out = 3.6864/2 =
1.8432MHz