Datasheet

SPI
Intel
®
Quark™ microcontroller D2000
Datasheet January 2016
238 Document Number: 333577-002EN
15.3.1.5 Slave Enable Register (SER)
This register is valid only when the SPI Controller is configured as a master device.
When the SPI Controller is configured as a serial slave, writing to this location has no
effect; reading from this location returns 0. The register enables the individual slave
select output lines from the SPI Controller master. Up to 16 slave-select output
signals are available on the SPI Controller master. You cannot write to this register
when SPI Controller is busy.
MEM Offset (B0001000) 10h
Security_PolicyGroup
IntelRsvd False
Size 32 bits
Default 0000_0000h
Bits Access
Type
Default Description PowerWell ResetSignal
31:4 RO 28'b0 Reserved 1 (RSVD1)
Reserved
3:0 RW/L 4'h0 Slave Select Enable Flag
(SER)
Each bit in this register
corresponds to a slave select
line (ss_x_n]) from the SPI
Controller master. When a bit
in this register is set (1), the
corresponding slave select line
from the master is activated
when a serial transfer begins.
It should be noted that setting
or clearing bits in this register
have no effect on the
corresponding slave select
outputs until a transfer is
started. Before beginning a
transfer, you should enable
the bit in this register that
corresponds to the slave
device with which the master
wants to communicate. When
not operating in broadcast
mode, only one bit in this field
should be set.
1: Selected
0: Not Selected